The present invention relates to semiconductor design technology, and more particularly to a semiconductor memory device having an on-die-termination device.
Generally, many new concepts have been proposed to rapidly control data transmission rate in double data rate (DDR) memory devices. Among the various concepts, the use of a termination resistor makes the memory device easily transmit signals with external devices.
However, if a resistance matching between the devices is not proper, a transmission signal may be reflected, thus leading to an error in signal transmission. Specially, when a fixed resistor is connected externally to the memory device, it is difficult to properly achieve the resistance matching because a resistance of the termination resistor in the memory device could be changed due to several factors such as aging of an integrated circuit (IC), temperature variation or difference in fabrication process. Accordingly, to equalize a total resistance of the termination resistor with external reference resistance, there has been suggested a technology where the resistance of the termination resistor is adjusted by controlling number of transistors to be turned on among a plurality of transistors connected in parallel.
Particularly, in a DDR3 synchronous dynamic random access memory (SDRAM), it is possible to control an on-die-termination (ODT) device to be activated when data are outputted to the outside through a write operation or at a desired time by applying a signal to an external pin.
A latency time taken from an input of an ODT signal applied through the external pin to actual activation/inactivation of a termination resistor is defined as an ODT latency. The ODT latency is classified into an ODT turn-on latency ODTLon and an ODT turn-off latency ODTLoff. The ODT latency is set down through a mode register set (MRS), and has a correlation with a write latency (WL), i.e., ODT latency=WL-2.
Hereinafter, a method of actually adjusting resistance of a termination resistor by applying an external ODT command will be described with reference to the accompanying drawings.
FIG. 1 illustrates a block diagram of a conventional semiconductor memory device having an ODT device.
Referring to FIG. 1, the conventional semiconductor memory device includes an input buffer 10, an additive latency (AL) delay unit 20, a domain crossing unit 30, a column address strobe (CAS) write latency delay unit 40, a driving control unit 50 and a plurality of termination resistors 60. The input buffer unit 10 receives an external ODT command EX_ODT to output an ODT command ODT_CMD. The AL delay unit 20 delays the ODT command ODT_CMD by a delay time corresponding to an additive latency using an internal clock ICLK as a reference clock. The domain crossing unit 30 converts an output signal ODT_AL of the AL delay unit 20 into a delay locked loop (DLL) clock domain signal. The CAS write latency (CWL) delay unit 40 delays a domain crossing signal A6 outputted from the domain crossing unit 30 by a delay time corresponding to the CAS write latency using the DLL clock DLL_CLK as a reference clock to thereby output a driving control signal ODT_EN. The plurality of termination resistors 60 are connected to an output pad in parallel and series. The driving control unit 50 turns on/off switches connected between a supply/ground voltage and the plurality of termination resistors 60 in response to the driving control signal ODT_EN.
FIG. 2 illustrates a block diagram of the domain crossing unit 30 in the ODT device of FIG. 1.
Referring to FIG. 2, the domain crossing unit 30 includes a reset controller 32, an initialization setter 31, a DLL clock counter 34, an ODT replica 33, an external clock counter 35, an edge detector 36 and a code comparator 37. The reset controller 32 generates an initialization signal A0 in response to a reset signal RE. The initialization setter 32 outputs an initial set value ST_CNT<0:2> corresponding to a CAS write latency information signal CWL. The DLL clock counter 34 maintains the initial set value ST_CNT<0:2> in response to the initialization signal A0 or counts the DLL clock DLL_CLK to output a DLL counting signal DLL_CNT<0:2>. The ODT replica 33 delays the DLL clock DLL_CLK by a delay time that a semiconductor memory device has. The external clock counter 35 counts an output clock of the ODT replica 33 in response to the initialization signal A0 to output an external clock counting signal EXT_CNT<0:2>. The edge detector 36 detects an edge of the output signal ODT_AL of the AL delay unit 20 to generate a start flag signal ODT_STP and an end flag signal ODT_ENP. The code comparator 37 outputs the domain crossing signal A6 at a point when the external clock counting signal EXT_CNT<0:2> at an activation point of the start flag signal ODT_STP or the end flag signal ODT_ENP is equal to the DLL counting signal DLL_CNT<0:2>.
For reference, the ODT replica 33 is used for compensating for the delay time of the semiconductor memory device, and synchronizing an activation point of the driving control signal ODT_EN with an external clock.
In this way, the conventional semiconductor memory device having the domain crossing unit 30 undergoes a clock domain conversion to synchronize the external ODT command EX_ODT, which is applied in synchronization with an external clock, with the DLL clock DLL_CLK because a turn-on point of the termination resistor can be synchronized with an output point of data only if signals for driving the ODT device should be synchronous with the DLL clock DLL_CLK containing an internal delay of the semiconductor memory device. Further, to adjust an output timing of a high-speed DRAM, the domain crossing unit 30 must operate in such a manner to secure a timing precisely.
The conversion procedure of the clock domain will be more fully described below with reference to a timing diagram.
FIG. 3 is a timing diagram illustrating an operation of the domain crossing unit 30 of FIG. 2. An operation of the conventional semiconductor memory device will be illustrated with reference to FIG. 3.
Referring to FIG. 3, the input buffer 10 determines a level of the external ODT command EX_ODT using a reference voltage VREF to thereby output an ODT command ODT_CMD. Thereafter, the AL delay unit 20 delays the ODT command ODT_CMD by a delay time corresponding to the additive latency information signal AL to output the additive ODT signal ODT_AL using the internal clock ICLK as a reference clock.
The reset controller 32 generates the initialization signal A0 in response to the reset signal RE. The initialization setter 31 outputs the initial set value ST_CNT<0:2> corresponding to the CAS write latency information signal CWL.
Subsequently, the DLL clock counter 34 maintains the initial set value ST_CNT<0:2> during the activation of the initialization signal A0. The DLL counting signal DLL_CNT<0:2> is maintained at a value such as a binary code ‘100’ of the initial set value ST_CNT<0:2>. Although not shown, since the DLL clock DLL_CLK is not toggled in response to the reset signal RE but maintained at a constant level, the external clock counter 35 is not enabled.
When the reset signal RE is deactivated, the reset controller 32 deactivates the initialization signal A0 in response to the deactivation of the reset signal RE.
As the initialization signal A0 is deactivated, the DLL clock counter outputs the DLL counting signal DLL_CNT<0:2> by counting the DLL clock DLL_CLK. The DLL counting signal DLL_CNT<0:2> increases according to the DLL clock DLL_CLK. Because the start point corresponds to the initial set value ST_CNT<0:2> as described above, the DLL clock counter 34 starts counting the DLL clock DLL_CLK from 5, i.e., a binary code ‘101’, as a decimal code when the DLL clock DLL_CLK is toggling. The ODT replica 33 delays the DLL clock DLL_CLK by an internal delay time of the semiconductor memory device.
Thereafter, the external clock counter 35 counts the output clock of the ODT replica 33 to increase the external clock counting signal EXT_CNT<0:2>. The counting of the external clock counter 35 always starts from ‘0’ of the decimal code.
The edge detector 36 generates the pulse type start flag signal ODT_STP in response to a rising edge of the additive ODT signal ODT_AL.
The code comparator 37 latches the external clock counting signal EXT_CNT<0:2> at the activation point of the start flag signal ODT_STP. As shown in FIG. 3, it is assumed that the external clock counting signal EXT_CNT<0:2> at this time point is 1 as the decimal code. The code comparator 37 keeps on comparing the latched external clock counting signal EXT_CNT<0:2> with the DLL counting signal DLL_CNT<0:2>, and thus activates the domain crossing signal A6 when the latched external clock counting signal EXT_CNT<0:2> and the DLL counting signal DLL_CNT<0:2> are equal to each other. In this case, the domain crossing signal A6 is activated when DLL counting signal DLL_CNT<0:2>_becomes 1 as the decimal code. That is, the code comparator 37 latches an input point of an external signal using the external clock as a reference clock, and then outputs the domain crossing signal A6 at the point for compensating for a delay of the semiconductor memory device by comparing the external clock and the DLL clock. Consequently, the conversion of the external signal into the DLL clock domain is achieved.
As such, the domain crossing unit 30 synchronizes the additive ODT signal ODT_AL with the DLL clock DLL_CLK to output the domain crossing signal A6.
The CWL delay unit 40 delays the domain crossing signal A6 by a delay time corresponding to the CAS write latency information signal CWL using the DLL clock DLL_CLK as a reference clock.
Because the driving control unit 50 turns on/off switches SW connected to the plurality of termination resistors 60 in response to the output signal ODT_EN of the CWL delay unit 40, the plurality of termination resistors 60 are selectively connected to the supply/ground voltage VDD/VSS, thus achieving impedance matching.
The conventional semiconductor memory device also undergoes the same procedure as described above even though the external ODT command EX_ODT is deactivated, thereby controlling all of the switches to be turned off. The edge detector 36 detects a falling edge of the additive ODT signal ODT_AL to generate a pulse type end flag signal ODT_ENP. The code comparator 37 latches the external clock counting signal EXT_CNT<0:2> in response to the end flag signal ODT_ENB to compare the latched external clock counting signal EXT_CNT<0:2> with the DLL counting signal DLL_CNT<0:2>. A subsequent procedure is identical to the above procedure, and hence further detailed description for it will be omitted herein.
In the above-described procedure, the conversion of signals into the DLL clock domain will be described in more detail again. For clock domain conversion, data is latched when the start flag signal ODT_STP or the end flag signal ODT_ENP is activated on the basis of the external clock. Herein, the external clock counting signal is latched in response to the start flag signal or the end flag signal. The latched external clock counting value is continuously compared with the DLL clock counting signal. Then, if the latched external clock counting value is equal to the DLL clock counting signal, the domain crossing signal A6 is activated. Through this procedure, the conversion of the clock domain is achieved to synchronize a signal, which was synchronized with the external clock, with the DLL clock.
To precisely latch the external clock counting signal EXT_CNT<0:2> at the activation point of the start flag signal ODT_STP or the end flag signal ODT_ENP, the start flag signal ODT_STP or the end flag signal ODT_ENP must be stably positioned within a time interval (hereinafter, referred to as a ‘counting window’) that one external clock counting signal EXT_CNT<0:2> occupies.
To this end, the output clock of the ODT replica has an optimized delay time by making a replica of the external clock, and thus the ODT replica 33 adjusts the start flag signal and the end flag signal to be positioned within the counting window of the external clock counting signal.
According to the conventional art, however, the start flag signal or the end flag signal may not be positioned within the counting window due to PVT (process, voltage and temperature) variations even though the ODT replica is designed to have the optimized delay time, thus leading to such a malfunction that the terminal resistor is not turned on/off at a time point set by standard specification.
Moreover, because a DDR3 DRAM actually supports an operating speed of 800 Mbps, 1,066 Mbps, 1,333 Mbps, 1,600 Mbps, etc., the procedure of adjusting the delay time of the ODT replica frequently occurs so as to secure an ODT latency at various operating speeds.